It is known that a semiconductor memory device comprises a matrix ("memory matrix") of memory cells located at the intersections of rows and columns of the matrix. The rows of the matrix are normally called "word lines", and the columns of the matrix are called "bit lines".
A Flash EEPROM memory cell is comprised of a floating gate MOS field effect transistor with drain and source electrodes, a control gate electrode and a floating gate electrode. The control gate electrode is connected to a respective word line of the memory matrix, the drain electrode is connected to a respective bit line, and the source electrode is connected to a reference potential.
The Flash EEPROM memory cell can be electrically programmed (or "written") and erased. During writing, electrons are transferred onto the floating gate electrode of the floating gate MOSFET by means of the so-called Channel Hot Electron ("CHE") effect. During erasing, electrons are removed from the floating gate electrode by means of Fowler-Nordheim tunneling.
The presence of electron charges on the floating gate electrode modifies the current/voltage characteristic of the floating gate MOSFET. In fact, the threshold voltage of the floating gate MOSFET varies according to the charge on its floating gate electrode. A written memory cell has a threshold voltage higher than that of an erased memory cell.
This difference in threshold voltages is exploited during reading mode to determine if a particular memory cell is erased or written. The word line to which the control gate electrode of the memory cell to be read is connected is raised to a voltage between the threshold voltage of an erased memory cell and that of a written memory cell, and the voltage of the bit line to which the drain electrode of the memory cell is connected is also raised. In these conditions, if the memory cell to be read is a written memory cell, it will not sink current, because the voltage on the control gate electrode of the memory cell is lower than its threshold voltage. If it is an erased memory cell, it will sink current, because the voltage on its control gate electrode is higher than its threshold voltage.
Known sense amplifier circuits substantially comprise current/voltage converters which convert the current sunk by the memory cell to be read into a voltage signal. Typically, this voltage signal is compared with a reference voltage signal obtained by current/voltage conversion of a reference current. The reference current is the current sunk by a so-called "reference memory cell", which is a floating gate MOSFET identical to those constituting the real memory cells, but having a predetermined threshold voltage, corresponding to the so-called "virgin state" (the erased condition achieved by a floating gate MOSFET after it has been submitted to Ultra-Violet light). In this way, all the spurious effects, such as statistical geometrical and process variations between memory cells, voltage variations, and so on, are eliminated, because they give rise to common-mode signals.
A specific problem of Flash EEPROM devices is related to the fact that Flash EEPROM devices are not erased on a per-byte basis, but on a per-sector basis. This means that many memory cells (from thousand to millions) are simultaneously submitted to electrical erasing. Consequently, it is not possible to individually control the behavior of each memory cell during erasing, the only feasible thing being a statistical approach. Slight differences in the electric characteristics of the conductive paths between the memory cells and the voltage rails, as well as in the geometry of the memory cells, determine a statistical distribution of the erasing time of the memory cells, and cause after erasing a dispersion of values of memory cells' electric parameters such as the threshold voltage, the memory cell current, and so on. Therefore, after repeated electrical writing and erasing cycles, some of the floating gate MOSFETs may happen to be overerased to the extent that their threshold voltages (normally positive) become negative.
The existence of even only one overerased, i.e., depleted, memory cell leads to the failure of the whole memory device. In fact, a depleted memory cell sinks a finite current even when it is not selected, i.e., when the voltage on its control gate electrode is zero. When an attempt is made to read a written memory cell belonging to the same bit line as the depleted memory cell, the current sunk by the latter causes the sense amplifier circuit to erroneously read the written memory cell as an erased memory cell. In other words, the current sunk by a depleted memory cell can be regarded as an offset current which adds to the current sunk by the memory cell to be read. This offset current causes an offset voltage to be superimposed on the output voltage signal of the current/voltage converter The offset voltage, if large enough, can be responsible for the incorrect reading of a written memory cell as an erased memory cell.